Latches and Flip Flops

Latches and flip flops are memory device. It can store previous values. There are two types of digital circuit, sequential and combinational digital circuit. Latches and flip flops are sequential digital circuit. When feedback from output is provided to input that circuit is called sequential circuit and in combinational circuit there is no any feedback from output.

SR latch

In this latch there are two inputs which are S and R and two outputs which are Q and inverted Q (Q). Where S sets the latch and R resets the latch means when S input is high, Q output is high and inverted Q is low and when R input is high, Q output is low and inverted Q is high. It stores one bit. It can be implemented using NOR or NAND gate.

SR latch using NOR gates
SR latch using NAND gate

Now let’s see the working of SR latch. If you have remembered this is the truth table of NOR gate.

You can see in the truth table if any input is high then the output of NOR gate is low. Now see the truth table of SR latch.

You can observe in the truth table of SR latch there are two condition labeled as memory. The reason is also shown in the truth table. You can clearly see if reset pin is triggered the inverted output is high and it remains high even if reset pin goes low. In the second condition set pin is high so Q output is high and it remains high even if set pin goes low. It shows that It can store one bit. The last condition when both input are same then it is not useful.

SR Flip-flop

There are three input terminals present in the SR flip flop. Here the clock pin is introduced which is third pin of this flip flop.

SR flip flop block diagram
Graphical symbol of SR flip flop

In the above figure, you can see there are another two NAND gates are connected in the SR latch with clock pin. If clock pin is high it will work same as an SR latch and when this is low then nothing happens.

Let’s see its truth table –

Excitation table of SR flip flop

In the excitation table we have to find out the inputs condition for present output and next output. Next output state is calculated using characteristics table in which the next state is calculated using previous state or present state. Let’s see how.

Now write the all possible combinations of present state and next state in another table and find out the input state for that output combination.

Let’s consider the first combination in excitation table. In the characteristics table you can see there are only two input combination is possible for which the present output state and next output state both are zero. In both that input combinations the S input is same which is low and R input changes. By using this process we will find inputs for all the combinations.

JK or master-slave flip flop

In SR flip-flop there are two basic problems occurs during switching.

  1. If S and R both pins are high, this is an invalid input and must be avoided.
  2. Like SR latch, during switching inputs when CLK is high, an incorrect latch can happen.

To avoid these problems the JK flip flop was developed. Here JK name was given in the honor of its developer who is Jack Kilby. Where J=S and K=R.

JK flip flop

Here you can see two input NAND gates of SR flip flop is replaced by 2 three input NAND gates and third input of both NAND gates is connected to Q and Q. This allow that invalid input in which S and R inputs are high in the form of “toggle action”, because the both input are now interlocked.

Symbol of JK flip flop

Master slave JK flip flop

In the JK flip flop SR latch is replaced by two SR latch in series configuration. One SR latch acts as “master” and another acts as “slave”. Master circuit triggers on the leading edge of clock pulses and slave circuit is triggered on the falling edge of clock pulses.

Master slave JK flip flop

Truth table of JK flip flop –

Characteristics table of JK flip flop

Where Q(n) = present or previous state

               Q(n+1) = next state

               Clock = high

Boolean equation for Q(n+1) using characteristics table –

Q(n+1) = Q(n)’J + Q(n)K’

Excitation table

D flip flop

D flip flop is a modified flip flop of SR flip flop or JK flip flop. D flip flop is obtained by connecting an inverter between input pins in SR or JK flip flop. It is  also called as data flip flop.

Implementing D flip flop
D flip flop symbol

This flip flop stores the data which is on the input.

Truth table of D flip flop –

Characteristics table of D flip flop

Where, Q(n) = previous state

               Q(n+1) = next state

               Clock = high

Excitation table

T flip flop

T flip flop toggles the output when a high input is provided to it, this is why it is also called as “toggle flip flop”.  By making a simple change in the JK flip flop we can design a T flip flop. Connecting J and K inputs together and giving them a single input is a T flip flop.

Truth table of T flip flop –

Characteristics table of T flip flop

Excitation table

So, Q(n+1) = Q(n) ⊕ T

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